This invention relates to semiconductor transistors and more particularly to a method of manufacture of bipolar transistors with enhanced emitter structures.
In the manufacture of bipolar transistors the trend in the semiconductor industry is to increase the switching speed performance of such transistors. To achieve enhanced switching speed performance, the layers through which the electrons traverse in the bipolar transistors must continually be decreased. Principally, these dimensions are the neutral base dimension and the collector-base space-charge dimension. Scaling the device also involves increasing the collector dopant concentration, which has the aforementioned effect of reducing the collector-base, space-charge dimension. In addition, scaling the device increases the current density at which the device reaches its peak operating speed.
Besides the positive effect of enhancing the switching speed of the device, there are problems in that the changes in the collector of the bipolar transistor have some potentially negative side-effects. One such problem is the increase of avalanche multiplication from the increased electric field in the collector-base space-charge region. A second problem is the increase of self-heating of the device. Such effects are described in more detail in G. Freeman, J.-S. Rieh, B. Jagannathan, Z. Yang, F. Guarin, A. Joseph, D. Ahigren, “SiGe HBT Performance and Reliability Trends through fT of 350 GHz,” Proc. IEEE Reliability Physics Symposium (Mar. 30, 2003). (hereinafter referred to as Freeman 2003) and M. Rickelt, H. M. Rein and, E. Rose, “Influence of Impact-Ionization Induced Instabilities on the Maximum Usable Output Voltage of Si-Bipolar Transistors,” IEEE Trans. on Electron Devices Vol. 48 n.4 p. 774–783 (April 2001) (hereinafter referred to as Rickelt 2001) One solution to the problem of the increasing self-heating of the device is to spread the current and thus the power over a larger region of the device, which reduces the thermal resistance and reduces the temperature rise of the device. Typically, as the current density of the device is increased due to the increased collector concentration, the width of the lithographically-defined emitter is reduced inversely with the current density increase, resulting in a similar current per unit length of the device.
Also, the increasing avalanche current must be accommodated in device design. In particular, as avalanche current increases with device scaling, side-effects, such as pinch-in phenomena, become predominant that limit the maximum attainable voltage in a device. The device design needs to be modified to accommodate this effect and to offer a design option that attains the highest possible voltage output capability.
In pinch-in, the device current is focused into the center of the device, where very high power densities can cause problems in device operation. The pinch-in effect is described well in Rickelt 2001.
FIGS. 1A–1C illustrate several aspects in the prior art of the phenomenon of side effects such as pinch-in as avalanche current increases.
FIG. 1A illustrates operation of a prior art bipolar device 10 with the collector C on the bottom, below the intrinsic base B, and with the emitter E formed in the top surface of the intrinsic base B. The device 10 is in the low collector voltage state, wherein avalanche does not occur, and the base current flows from the base B into the emitter E of the device 10. FIG. 1B illustrates the prior art device 10 of FIG. 1A in the moderate avalanche condition, wherein the base current flows relatively uniformly up from the collector C through the intrinsic base B and out of the base terminal of the device 10. FIG. 1C illustrates the device 10 of FIG. 1A under the strong avalanche condition, wherein the exiting base current creates a distribution of internal base-emitter voltage, such that the center of the device is turned on more strongly than the external portion of the collector C of the device 10 whereby the current lines in the drawing are absent from the external portion of collector C. This latter condition is the undesirable pinch-in condition.
Thus there is a need to further enable scaling of such devices to deliver higher performance through providing a device design that counters the trends towards the problem of the avalanche effect and the problem of self-heating. To counter the kind of avalanche effect described above, in the past it has been suggested that the base resistance may be further reduced to compensate for the increased avalanche (Freeman 2002). However, the problem is that methods or structures, which enhance the voltage capability have not been described.
To accommodate the current density increase, a reduction in the stripe width continues to be a goal. Yet very narrow dimensions are increasingly difficult to attain. FIG. 2 is a graph showing an empirical trend in the prior art of current density versus device design peak fT. The graph of FIG. 2 illustrates the increase in current density by generation (Freeman 2002). Note for instance that transitioning from the 200 GHz device design to the 350 GHz device design results in a current density increase from 12 mA/μm2 to 20 mA/μm2. Considering that the device dimension for a 200 GHz device is 0.12 μm, a straightforward scaling of the emitter width would result in an emitter dimension of 0.072 μm. Due to perimeter injection from the emitter, we find that the current does not scale directly with emitter width, resulting in the desire to scale the dimension to yet smaller dimensions. Thus it is desirable to provide as small an emitter dimension as is possible. Small dimensions may be obtained through advanced lithography techniques. Yet such techniques are costly and involve constraints such as pattern density, minimum dimensions, and mask data preparation complexities.
U.S. Pat. No. 5,866,462 of Tsai et al. entitled “Double-Spacer Technique for Forming a Bipolar Transistor with a Very Narrow Emitter” describes a larger lithography method for defining a smaller dimension emitter. The Tsai et al. technique involves starting with a substrate on which a layer of base-contact polysilicon and a layer of dielectric film (a Low Temperature Oxide (LTO)) thereabove. First, an opening is established in the LTO dielectric film. Next, a narrower opening is defined by creating a first set of dielectric sidewall spacers on the walls of that opening. Then an emitter opening is etched through the base-contact polysilicon. Next a second set of dielectric sidewall spacers are formed inside the emitter opening defining a narrowed emitter opening. Then, polysilicon is applied through the narrowed emitter opening to contact the emitter region in the substrate. The resultant narrowed opening has the dimension of the original opening less twice the sidewall spacer dimension. Such a resultant dimension may not be made so small that the variation in size of the original opening together with the variation in size of the sidewall spacer may subtract substantially from the expected size, thus rendering the device not useful. Thus there is an issue with process control and with minimum dimensions achievable with the structure described by Tsai et al. Furthermore, the large width to height aspect ratio would likely result in a significant emitter resistance, which is detrimental to device performance.
U.S. Pat. No. 6,380,017 of Darwish et al. entitled “Polysilicon-Edge, Base-Emitter Super Self-Aligned, Low Power, High Frequency Bipolar Transistor and Method of Forming the Transistor” describes an alternate approach is to use a sidewall spacer to define the emitter dimension. Yet the approach provided by Darwish et al. does not provide for an emitter contact over the emitter region, which is needed to maintain a low emitter resistance for high performance bipolar transistor operation.